Metastability: What is Metastability?[ common interview Question ]

The most common question which i faced during my interviews is regarding Metastability. To discuss this issue, let me consider an example of Inverter logic been driven with input Vin in two different scenarios,
scenario1:  Vin driven with sufficent delay and input voltage.

Figure 3.1 Inverter driven with sufficient delay

From Scenario1, the input Vin is driven with sufficient delay, any Vin input value ranging above Vmax causes logic 1 and Vin value ranging below Vmin causes logic 0.  As input of Inverter starts rising from minimum value to maximum value, the capacitance associated at the output node starts discharing,with some delay, the output of the inverter starts declining. Sufficient time delay is provided for the inverter output to completely decline to logic value zero, hence we did not see any meta-stable value. No metastable state can occur if inverter is driven with sufficient delay.

scenario2:  Vin driven with insufficient delay.

                                             Figure 3.2 Inverter driven with insufficient delay

From Scenario2, the input Vin is driven with insufficient delay, As Vin starts rising, the output node capacitance starts discharging, since due to insufficient delay in the input the output before reaching Vmin again starts charging i.e, Vout starts rising again, the signal in this scenario is neither a logic 1 or logic 0 called as metastable state. The Vin driven with insufficient delay causes a mestable state.

BIST- Built In Self Test [ Conventional Architecture ]

BIST is a self test mechanism used to observe and control CUT [Circuit Under Test] and produce the result pass or fail. Conventional BIST architecture consists of LFSR [Linear Feedback Shift Register], CUT, MISR [Multiple Input Signature Register], ROM[storage- Golden Values] and Compactor[Analyzer] were these blocks sit on the chip. BIST logic is a additional test logic which occupy the area on the chip. The Conventional BIST architecture is represented in Figure 2.1 as shown below,

During BIST mode, the patterns are generated from the LFSR. These patterns are applied to the scan inserted CUT, the scan chain inputs are driven by the LFSR patterns. Scan chains are operated in Shift and capture mode, the output response from the scan chains are converted to signature using MISR based Compaction. The Signature from the ROM and MISR is compared using a Analyser, The final outcome of the BIST mode is Result Pass or Result Fail, which is triggered by the Analyser. 

Basics Of VLSI Chip Testing - [ Need For VLSI Chip Testing - Why & What ]

Importance of VLSI Chip Testing:

Nowadays testing have become an important aspect for every chip being fabricated. To analyse it consider a simple example of car air bag activator control system as shown in the figure 1.1.

Figure 1.1 Car air bag activator control System

The system is designed in such a way that whenever a car is subjected to crash, either of the crash sensor 1 or crash sensor 2 gets enabled, there by an airbag activator signal is generated to activate the air bag which saves the lives of the people. From figure 1.1 consider a simple logic implementation of car crash sensor control system by simple NOR gate and Inverter gate in series.

Table 1.1 Truth table for air bag activator control system

When either of the inputs to NOR gate goes high, the output of NOR gate is 0 and the inverted output will be 1, which activates the air bag. The truth table for air bag activator is as shown in table 1.1.

Figure 1.2 Transistor and physical layout of inverter

Assume this simple airbag control system is being fabricated, say inverter logic in the system is been fabricated. Normally assumption for inverter physical implementation would be like as shown in figure 1.2.

As due to some manufacturing imperfections at different levels of fabrication, from figure 1.3 may be at metal deposition level, an extra metal would be deposited between output and Vss of inverter or at etching level certain path between output and Vss would not be etched properly.

Such direct paths between Vss and output will always lead the output to stuck at 0, termed as a defect in inverter. If such an inverter is used in logic block of car airbag activator control system, the air big will never get activated, such that system is subjected to failure, this is a system failure.

Figure 1.3 Inverter layout due improper etching.

costs the lives of number peoples. The truth table for such a failure system is shown in table 1.2. Even though either of the crash sensors are going high, still air bag activator remains 0 due to defect at the output. Hence there must be a criteria or methodology to check such defects after fabrication. The solution is provided by subjecting chip after fabrication to testing.

FOR TUTORIAL VIDEO OF ABOVE DISCUSSION CLICK ON THE LINK BELOW

https://www.youtube.com/watch?v=ztT3ttaCtuE

https://www.youtube.com/watch?v=ztT3ttaCtuE