BIST- Built In Self Test [ Conventional Architecture ]

BIST is a self test mechanism used to observe and control CUT [Circuit Under Test] and produce the result pass or fail. Conventional BIST architecture consists of LFSR [Linear Feedback Shift Register], CUT, MISR [Multiple Input Signature Register], ROM[storage- Golden Values] and Compactor[Analyzer] were these blocks sit on the chip. BIST logic is a additional test logic which occupy the area on the chip. The Conventional BIST architecture is represented in Figure 2.1 as shown below,

During BIST mode, the patterns are generated from the LFSR. These patterns are applied to the scan inserted CUT, the scan chain inputs are driven by the LFSR patterns. Scan chains are operated in Shift and capture mode, the output response from the scan chains are converted to signature using MISR based Compaction. The Signature from the ROM and MISR is compared using a Analyser, The final outcome of the BIST mode is Result Pass or Result Fail, which is triggered by the Analyser.