Metastability: What is Metastability?[ common interview Question ]

The most common question which i faced during my interviews is regarding Metastability. To discuss this issue, let me consider an example of Inverter logic been driven with input Vin in two different scenarios,
scenario1:  Vin driven with sufficent delay and input voltage.

Figure 3.1 Inverter driven with sufficient delay

From Scenario1, the input Vin is driven with sufficient delay, any Vin input value ranging above Vmax causes logic 1 and Vin value ranging below Vmin causes logic 0.  As input of Inverter starts rising from minimum value to maximum value, the capacitance associated at the output node starts discharing,with some delay, the output of the inverter starts declining. Sufficient time delay is provided for the inverter output to completely decline to logic value zero, hence we did not see any meta-stable value. No metastable state can occur if inverter is driven with sufficient delay.

scenario2:  Vin driven with insufficient delay.

                                             Figure 3.2 Inverter driven with insufficient delay

From Scenario2, the input Vin is driven with insufficient delay, As Vin starts rising, the output node capacitance starts discharging, since due to insufficient delay in the input the output before reaching Vmin again starts charging i.e, Vout starts rising again, the signal in this scenario is neither a logic 1 or logic 0 called as metastable state. The Vin driven with insufficient delay causes a mestable state.

BIST- Built In Self Test [ Conventional Architecture ]

BIST is a self test mechanism used to observe and control CUT [Circuit Under Test] and produce the result pass or fail. Conventional BIST architecture consists of LFSR [Linear Feedback Shift Register], CUT, MISR [Multiple Input Signature Register], ROM[storage- Golden Values] and Compactor[Analyzer] were these blocks sit on the chip. BIST logic is a additional test logic which occupy the area on the chip. The Conventional BIST architecture is represented in Figure 2.1 as shown below,

During BIST mode, the patterns are generated from the LFSR. These patterns are applied to the scan inserted CUT, the scan chain inputs are driven by the LFSR patterns. Scan chains are operated in Shift and capture mode, the output response from the scan chains are converted to signature using MISR based Compaction. The Signature from the ROM and MISR is compared using a Analyser, The final outcome of the BIST mode is Result Pass or Result Fail, which is triggered by the Analyser.